1. Field of the Invention
The present invention relates to a bus configuration circuit suitable for use in an information processing system, which comprises a plurality of master modules, a plurality of slave modules and bus modules which connect among these master and slave modules.
2. Description of the Related Art
There has recently been in the limelight, a platform design wherein IPs (Intellectual Properties) each having functions necessary for the periphery of a platform in which basic modules such as a CPU (microprocessor), a memory, an interrupt controller, etc. are built therein and which guarantees the reliability of operation, are disposed by using the platform. Since the IPs (Intellectual Properties) corresponding to functional blocks are disposed on the periphery of the platform via buses or bus modules according to purposes upon the platform design, each single design becomes unnecessary and the shortening of delivery times can be realized. The execution of the above-described design has been described in, for example, the following Patent Document 1.
Japanese Laid Open Patent Application No. 2000-276358.
However, there has recently been a demand for execution of multiprocessoring or multilayer busing or the like with a view toward improving the performance of an information processing system. Thus, there has been a need for newly considering a platform corresponding to the multiprocessoring or multilayer busing. FIG. 3 shows a conventional system configurational example using an AHB (Advanced High-Performance Bus) of AMBA (Advanced Microcontroller Bus Architecture) corresponding to general bus specs. A schematic block diagram of a system configurational example where multiprocessoring has been done, is shown in FIG. 6, and a block diagram of a system configurational example where multilayer busing has been done, is shown in FIG. 7.
As shown in FIG. 6, there is known an example for realizing multiprocessoring by using a platform 2 shown in FIG. 3 in plural form as one method of multiprocessoring. A selector 301 performs access arbitration among a master module M211 provided within a platform 210, a master module M221 provided within a platform 220 and a master module M12 and obtains access to a slave module S212, S213, S222, S223, S23 or S24. An access response issued from the slave module S212 or S213 provided within the platform 210, the slave module S222 or S223 provided within the platform 220, or the slave module S23 or S24 is selected by a selector 302, which is returned to all the master modules. In this case, the platform 220 and the platform 210 are precisely the same as the platform 2 shown in FIG. 3. Since the already-existing basic modules are reused, system design in a short period is enabled.
Further, the multilayer busing is a system wherein bus layers are respectively assigned to a plurality of master modules as referred to as a multilayer AHB, access arbitrations among the respective layers and respective slave modules are individually performed so that plural master module-to-slave module accesses can be performed simultaneously, thereby improving system performance.
FIG. 7 illustrates a bus configurational example using the platform 2 and multilayer AHB shown in FIG. 3. The platform 210, a master module M12 and a master module M13 are respectively assigned to bus layers of a layer 317, a layer 318 and a layer 319, as shown in FIG. 7. A selector 314 performs arbitration among accesses from the respective layers and thereby obtains access to a slave module S21 or S22 provided within the platform 210. A selector 315 also performs arbitration among accesses from the respective layers and thereby obtains access to a slave module S23. Also a selector 316 performs arbitration among accesses from the respective layers and thereby obtains access to a slave module S24. Access responses issued from the slave modules S21, S22, S23 and S24 are respectively selected by selectors 311, 312 and 313, which in turn are returned to the master modules M11, M12 and M13 respectively. When simultaneous access from the different master modules to the same slave module occurs, an access arbitration wait takes place by the selector 314, 315 or 316, so that the master modules are capable of merely performing access in order. However, plural master module-to-slave module accesses can simultaneously be done unless the simultaneous access to the same slave module occurs.
However, when such multiprocessoring as shown in FIG. 6 is performed where the platform 2 takes such a configuration as shown in FIG. 3, the slave modules S212 and the slave module S222 exist in the same address space on a system because the platform 220 is just the same module as the platform 210. Similarly, the slave module S213 and the slave module S223 exist in the same address space, thus causing a problem that the system fails to operate in the normal manner.
When such multilayer busing as shown in FIG. 7 is performed where the platform 210 takes such a configuration as shown in FIG. 3, multilayering is carried out outside the platform 210 but only one bus right exists in the platform 210. Therefore, when the master module M12 or M13 provided outside the platform 210 obtains access to the slave modules S21 and S22 provided within the platform 210, it cannot obtain access thereto unless the bus right in the platform 210 is obtained. Thus, while the master module M12 or M13 is being accessed to the slave modules S21 and S22, accessing is awaited even if an access destination of the master module M11 provided within the platform 210 is not intended for the slave module S21 or S22. Therefore, a problem arose in that a performance improvement enough for the master module M11 could not be obtained.